Many electronic systems utilize a high-frequency signal such as a clock signal that must be supplied to a large number of components within the system. In these situations, buffer circuits are typically needed to adequately drive the large number of components receiving the clock signal and to isolate a circuit generating the high frequency clock signal, such as a crystal oscillator, from the large number of components. This isolation is needed so that the circuit generating the high frequency clock signal is not unduly loaded by these components, which can result in undesirable variations in the high-frequency clock signal such as variations in frequency, amplitude and phase of the clock signal.
FIG. 1 illustrates a conventional architecture for buffering a clock signal that is utilized in cellular telephones. In this architecture, a crystal oscillator 100 generates a high-frequency clock signal CLK that is supplied to a plurality of parallel-connected buffers 102. Each buffer 102 generates a corresponding buffered clock signal BCLK in response to the CLK signal from the oscillator 100 and supplies this buffered clock signal to corresponding RF circuitry 104, analog baseband circuitry 106, and digital baseband circuitry 108 within the cellular telephone. The buffers 102 are utilized and are needed because if the crystal oscillator 100 were directly connected to the RF circuitry 104, analog baseband circuitry 106, and digital baseband circuitry 108 the resulting load on the oscillator could cause the frequency, amplitude, and phase of the CLK signal to undesirably vary. The buffers 102, however, can consume an undesirable amount of power and can become more complex circuits as supply voltages (not shown) provided to these buffers and other components in the cellular telephone are reduced to lower the overall power consumption of the telephone.
Other known architectures have been utilized for buffering high-frequency clock or other signals, such as a plurality of series-connected inverters as shown in FIG. 2. In this approach, a high-frequency clock signal CLK propagates through a plurality of series-connected inverters to generate a buffered clock signal BCLK, with two such inverters 202 and 204 being shown in the example of FIG. 2. Note that went inverters are utilized the buffered clock signal BCLK is a square wave signal even when the applied clock signal CLK is a sinusoidal signal. This square wave BCLK signal includes high-frequency harmonics which can cause unwanted interference in RF circuitry and other circuitry receiving the buffered clock signal.
FIG. 3 is a simplified schematic illustrating another conventional architecture for buffering a high-frequency clock signal CLK through a high bandwidth unity gain amplifier 300 to generate a buffered clock signal BCLK. In this situation, the amplifier 300 BCLK signal is also a sinusoidal signal and thus the same problems with unwanted harmonics do not exist when compared to the approach of FIG. 2. Since the CLK signal is a high frequency signal, however, the amplifier 300 must accordingly be a high bandwidth amplifier that may consume a relatively large amount of power.
FIG. 4 is a simplified schematic of another conventional approach for buffering a clock signal through a source-follower amplifier 400. The source-follower amplifier 400 includes an NMOS transistor 402 connected in series with the current source 404 between a supply voltage VDD and ground. In response to a high-frequency clock signal CLK applied to the gate of the NMOS transistor 402 the transistor develops a buffered clock signal BCLK on its source. With the source follower 400, the voltage swing of the BCLK signal is limited by the gate-to-source voltage Vgs of the NMOS transistor 402 and if the lowest level of the CLK signal is less than the gate-to-source voltage the buffer clock signal will be clipped. As the magnitude of the supply voltage Vdd decreases, the gate-to-source voltage Vgs of the NMOS transistor 402 becomes a significant hindrance to proper operation of the source follower 400.
There is a need for improved circuits, systems, and methods for buffering high-frequency signals such as high-frequency clock signals.